1. Purpose of the gate
The first wafers with the custom layers are back, and the first parts are packaged and ready for test.
First silicon on a structured ASIC device arrives sooner than on a full custom chip, because only the custom layers were processed on wafers that were already banked. The review is short but practical: are wafers and packaged parts here, is the test program and hardware ready, and is the plan for the first tests clear.
It confirms the wafers are from the allocated lots and base revision, and that wafer level data from the foundry, both the original acceptance data from banking and the data from custom layer processing, is available and within limits.
It agrees what will be tested first, usually continuity, test structures, scan and basic function, then memories through their self-test, then input and output behaviour, and who decides when parts are good enough to become samples for the customer.
Because the base has already been validated and qualified on test designs, early failures are more likely to lie in the custom layers, the design or the test program than in the base. The review agrees how failures will be diagnosed, using scan diagnosis to locate failing logic, and when a suspected base issue is escalated to the platform team, since a base issue would affect other customers too.
The customer is waiting for samples, and a converted design's customer is often waiting to replace FPGAs in a product already shipping. The review agrees how often the customer hears about bring-up progress and what they will be told if it slips.
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