1. Purpose of the gate
The idea of a base array platform, the customer designs it would serve and the turnaround and cost it would offer are accepted, and a team is funded to define it.
Concept approval is the first commitment of money and people to a structured ASIC platform. It is a bet on a gap between two alternatives customers already have: staying on an FPGA in volume, which keeps flexibility but costs more per unit and uses more power, and a full custom chip, which costs least per unit at high volume but carries a full mask set, a long schedule and a large engineering charge. The platform must offer something clearly between the two for enough customers to pay back a base array that is designed, taped out and qualified once.
The gate does not judge the architecture; there is none yet. It judges whether the gap is real and specific: which kinds of customer designs would use the platform, roughly how large they are and how many units they ship, why those customers would not stay on an FPGA or go full custom, and whether the organisation can run both halves of the lifecycle, the platform and the stream of customer designs on it.
Reviewers should leave able to say in a sentence who the platform is for and why it wins against those two alternatives. If they cannot, the concept is not yet clear enough to define, however attractive the market looks.
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