Designing how the chip meets its security requirements: the hardware root of trust, the secure boot chain, key storage, key management and provisioning, secure debug and device lifecycle states, isolation between trusted and untrusted software, cryptographic accelerators and their interfaces, random number generation, and the countermeasures against side-channel and fault injection attacks.
This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.