1. Purpose and scope
Every chip built on a node inherits the wear-out behaviour of its transistors, gate dielectrics, contacts and wiring. Customers qualify their own products, but they cannot test the node's intrinsic mechanisms one by one, and they should not have to. This stage proves, with accelerated stress tests on structures designed for the purpose, that each mechanism meets the lifetime target set in the technology definition under the use conditions the design kit allows.
The result has two uses. The technology qualification report is the formal evidence that the process is qualified, a condition of risk production and of every customer product qualification. The reliability design rules turn the same results into limits designers can apply: current density limits for wires and vias, voltage and temperature limits for each device type, and guard bands for ageing in timing.
In scope: the reliability test plan, wafer-level and packaged stress tests on qualification vehicles, lifetime modelling, failure analysis, ESD and latch-up characterisation, and the reliability rules. Out of scope: qualification of individual customer products, which customers run in Risk Production with the foundry's support.
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