A silicon photonics product, from its application and link budget through photonic and electronic co-design, the photonic design kit and component libraries, the choice of laser integration, circuit design, layout and photonic verification, shuttle and product tape-outs, wafer-level optical test, packaging and fibre attach, reliability qualification and system validation to production ramp and end of life. The output is an optical engine, transceiver or co-packaged optics product, or an optical sensing chip.
Silicon photonics and optical interconnect lifecycle: 13 stages, 14 gates of its own and 6 hand-offs to the Product lifecycle, from Application & Link Budget to End of Life.
13 stages, 14 gates of its own and 6 hand-offs to the Product lifecycle, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
In collaboration with The Digital Electronics Blog (opens in a new tab)
A dashed sign with a TR tag is a technical readiness review gate.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Deciding what the optical link must do and proving on paper that it can: the application (data centre interconnect, co-packaged optics beside a switch or accelerator, on-board or pluggable optics, or optical sensing), the reach, data rate, lane count, wavelength plan and modulation format, and the link budget that adds up laser power, coupling losses, waveguide and component losses, receiver sensitivity and the margin left for ageing and temperature, and the published optical interface standards and multi-source agreements the product must conform to, such as IEEE 802.3 optical PHYs or Optical Internetworking Forum implementation agreements.
Concept approval gate, owned by the Product lifecycle (Concept approval)Link budget baselined gate
Fixing the architecture of the photonic integrated circuit and the electronic circuits that drive and read it as one system: modulator and driver pairing, photodetector and transimpedance amplifier pairing, the electrical interface to the host SerDes, thermal tuning and wavelength control, the integration approach (monolithic, or a separate electronic die joined in two and a half or three dimensions) and the foundry platform.
TR1: Platform and coupling feasibility gateTR1, technical readiness reviewArchitecture freeze gate
Making sure every building block the circuit needs exists, is modelled and can be trusted: the foundry's photonic process design kit, its waveguides, bends, crossings, splitters, grating and edge couplers, modulators, photodetectors, heaters and filters, the compact models that let circuit simulation predict them, and any custom components the product needs that the kit does not provide.
Working out in detail how light gets onto the chip, with the laser source and integration approach chosen at the architecture freeze, because silicon itself does not emit it efficiently: an external laser source connected by fibre, a laser die flip-chip bonded or butt-coupled to the photonic die, heterogeneous integration of laser material on the wafer, or transfer printing.
Designing the photonic circuit from library components and simulating it together with its drivers, receivers and control loops: optical circuit simulation in the frequency and time domains, electro-optic co-simulation of the full transmitter and receiver, thermal simulation of heaters and crosstalk, wavelength and bias control, and statistical analysis of how process variation moves the wavelength, loss and bandwidth.
Drawing the photonic layout, much of it curved, and checking it: waveguide routing with controlled bends and crossings, placement of fibre couplers at the die edge or surface, heater and metal routing, design rule checks that understand curved shapes, layout versus schematic checks for photonic devices and their connectivity, and post-layout simulation of the drawn circuit, alongside the layout of the electronic die.
Releasing the design to the photonic foundry, on a multi-project wafer shuttle for early cycles or on a dedicated run for product: final checks, fill and density, test structures for optical and process monitoring, the run booking and the foundry's acceptance of the database, with the electronic die released on its own process at the same time where the product has one.
Measuring the photonic wafers before they are diced: optical probing through grating couplers or other test access, insertion loss, modulator bandwidth and efficiency, photodetector responsivity and dark current, heater tuning and wavelength, correlation of the measurements with the compact models, and the known good die criteria that decide which dies go on to assembly.
First light on wafer gateKnown good die criteria released gate
Assembling the photonic die with its electronic die, laser and fibres into a package or module: die attach and bonding, fibre array or connector attach with active or passive alignment, adhesives and their cure, optical and thermal design of the package, co-packaging beside a host chip where the application calls for it, and the assembly process capability that volume will depend on.
Assembly process qualified gateEngineering samples gate, owned by the Product lifecycle (Engineering samples)
Showing that the optical parts will last in the field: laser ageing and wear-out, the stability of coupling and adhesives under temperature cycling, damp heat and mechanical shock, photodetector and modulator drift, the electronic die's own qualification to JEDEC practice, and for optoelectronic modules the generic reliability assurance practice the industry publishes, such as Telcordia GR-468.
Proving the link works in the system it was designed for: bit error rate and margin across temperature and supply, interoperability with other vendors' optics and with the electrical interfaces of the host, conformance to the applicable published specifications such as IEEE 802.3 optical PHYs, Optical Internetworking Forum agreements or a module multi-source agreement, module management, laser safety classification under IEC 60825, product compliance declarations, thermal behaviour in the real enclosure and customer qualification.
System validated gateTR3, technical readiness reviewProduction release gate, owned by the Product lifecycle (Production release)
Building in volume: wafer supply from the photonic and electronic foundries, laser and fibre supply, assembly throughput, which is often limited by optical alignment, optical test time, yield learning across wafer test, assembly and final test, statistical process control and continuous improvement while demand grows.
Volume ramp gate, owned by the Product lifecycle (Volume ramp)
Withdrawing the product in an orderly way: a last-time buy, last builds while laser, fibre, wafer and assembly supply still exist, support for customers moving to the next generation of optics, and an archive of the design, test and qualification data so questions about shipped parts can still be answered.
Last-time buy gate, owned by the Product lifecycle (Last-time buy)Last-time ship gate, owned by the Product lifecycle (Last-time ship)
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.