1. Purpose and scope
A process design kit is the contract between a process and every chip designed on it. Designers never see the wafers being built while they work; they see the models, rules, decks, technology files, PCells, symbols and libraries in the kit. The purpose of this stage is to decide, before any of that content is written, what the kit must contain, which design work each release must support, how mature each release must be, and who owns each part.
Planning turns the approved technology definition from the process node lifecycle into a kit plan. The technology definition says which transistors, threshold voltage flavours, IO voltages, passives, special devices and metal stack options the node offers, and states the rule intent behind the tightest layers. The kit plan says which of those are modelled and released in which kit release, which tool categories the kit is checked in, which standard cell architectures, IO libraries and memory compilers are built, and what the release maturity criteria are for each release.
In scope: the PDK scope and charter, the customer and design flow requirements, the tool support matrix, the foundation IP plan, the release maturity criteria, the PDK development plan and the kit source repository. Out of scope: writing rules, fitting models, coding decks and laying out cells, which belong to the stages that follow. Planning is revisited at every release, but the baseline set here is under change control from the PDK plan and tool support baselined gate onwards.
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