1. Purpose and scope
A memory die only reaches a system inside a package, and for high bandwidth memory inside a stack of dies on a base die. Stacking multiplies risk: one bad die spoils a whole stack, so every die must be known good before it is bonded, and the stack must be tested and repaired through the test access the design provided. Heat must leave through the stack, and the stack must stay flat enough to be assembled beside a processor on an interposer or bridge.
This stage proves the known good die flow, the stack assembly process and stack test, and releases packages and stacks that meet their targets. It closes at Known good stack release, after which stacks can be offered to system makers and to the package and chiplet teams who integrate them. The stack design itself was frozen earlier, at Stack design freeze in Die Design & Verification.
In scope: known good die test, via reveal, thinning and bumping, stacking and bonding, stack test and repair, thermal and warpage modelling, package design for discrete parts, genealogy and the hand-over to integrators. Out of scope: package and stack qualification, which belongs to Component Qualification (JEDEC), and the integrator's own package development, which the chiplet and packaging lifecycle covers.
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