Chip lifecycle / Medical lifecycle / System, Chip & Software Architecture with Risk Controls

System, Chip & Software Architecture with Risk Controls

Partitioning the device into hardware, chips, software and user interface, choosing risk control measures and placing them in the architecture, defining patient and operator protection and isolation, assigning a software safety class, writing the chip specification for any custom silicon and building the threat model.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^A03 Design Inputs & Hazard Analysis

^O04 System, Chip & Software Architecture with Risk ControlsYou are here

^A05 Hardware & Chip Design and Implementation

Device, quality and regulatory milestones

Hardware, chip and software milestones

TFTR1TR1: Technology feasibility DPDesign plan approved DIDesign inputs approved ARArchitecture and risk controls approved TOTR2Chip tape-out and board design release

Program and product management^A

Quality management system and design controls^DA

0.3^A

Systems engineering and requirements^AO

0.3

0.5

Medical chip design^A

0.3

0.5

0.8

Chip verification and safety analysis^A

0.3

0.5

0.8^A

Board and device hardware^A

0.3

0.5

0.8^A

Device software (IEC 62304)^D

0.3

0.5

Product cybersecurity^A

0.3

0.5

Electrical safety, EMC and compliance testing^A

0.0

0.3

0.5

Usability engineering and design validation^A

0.3

0.5

Manufacturing, test and supply^A

0.0

0.3

Key0.0Planned0.3Early draft0.5Draft0.8Feature complete1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: System, Chip & Software Architecture with Risk ControlsAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

Show this chart as a list

Stages

Device, quality and regulatory milestones

Hardware, chip and software milestones

TR1: Technology feasibility (TF) (technical readiness review TR1)
Design plan approved (DP)
Design inputs approved (DI)
Architecture and risk controls approved (AR)
Chip tape-out and board design release (TO) (technical readiness review TR2)

Disciplines

Program and product management^A
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Design and development plan, schedule and review points approved, with the programme tracked against them through the design inputs and the architecture.
- System, Chip & Software Architecture with Risk Controls: maturity 0.3, Early draft. Design and development plan, schedule and review points approved, with the programme tracked against them through the design inputs and the architecture.
- Hardware & Chip Design and Implementation: maturity 0.5, Draft. Design implementation and verification tracked across hardware, chip and software, with test laboratory slots and usability studies booked.
Regulatory affairs^A
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Regulatory strategy and applicable standards agreed, with the evidence each standard and requirement needs mapped to the design inputs.
- System, Chip & Software Architecture with Risk Controls: maturity 0.5, Draft. Technical documentation structure drafted against the approved architecture, with design outputs filed as they are released.
- Hardware & Chip Design and Implementation: maturity 0.5, Draft. Technical documentation structure drafted against the approved architecture, with design outputs filed as they are released.
Quality management system and design controls^DA
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Quality plan approved and the design history file opened under document control, with the design inputs approved at a formal design review.
- System, Chip & Software Architecture with Risk Controls: maturity 0.5, Draft. Design outputs from the hardware, chip and software design reviews filed, with supplier and purchasing controls running.
- Hardware & Chip Design and Implementation: maturity 0.5, Draft. Design outputs from the hardware, chip and software design reviews filed, with supplier and purchasing controls running.
Risk management^A
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Risk management plan approved with its acceptability criteria, and the first hazard analysis issued with the design inputs.^A
- System, Chip & Software Architecture with Risk Controls: maturity 0.5, Draft. Risk controls chosen and allocated in the architecture, with hardware failure modes analysed as the design takes shape.
- Hardware & Chip Design and Implementation: maturity 0.5, Draft. Risk controls chosen and allocated in the architecture, with hardware failure modes analysed as the design takes shape.
Systems engineering and requirements^AO
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Technology feasibility shown, then the design input requirements approved and traced to user needs, with essential performance and basic safety defined.
- System, Chip & Software Architecture with Risk Controls: maturity 0.5, Draft. System architecture and interfaces approved with every risk control allocated, and the trace from inputs to outputs being built.
- Hardware & Chip Design and Implementation: maturity 0.5, Draft. System architecture and interfaces approved with every risk control allocated, and the trace from inputs to outputs being built.
Medical chip design^A
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Custom chip concept outlined from the design inputs: the functions to integrate, the process options and the chip-level risk controls.
- System, Chip & Software Architecture with Risk Controls: maturity 0.5, Draft. Chip specification and chip risk control requirements approved at the architecture review, with the chip design under way.
- Hardware & Chip Design and Implementation: maturity 0.8, Feature complete. Chip design complete and taped out after pre-silicon verification and sign-off checks, with first silicon still to come.
Chip verification and safety analysis^A
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Chip verification strategy outlined with the chip concept: the safety mechanisms to verify, the fault models and the mixed-signal platforms.
- System, Chip & Software Architecture with Risk Controls: maturity 0.5, Draft. Chip verification plan and environment built against the chip specification: testbench, models, checkers and the fault injection set-up.
- Hardware & Chip Design and Implementation: maturity 0.8, Feature complete. Pre-silicon verification and fault injection closed on the final design, with the chip verification report approved for tape-out.^A
Board and device hardware^A
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Board, power and isolation concept outlined against the design inputs, with the means of patient and operator protection chosen.
- System, Chip & Software Architecture with Risk Controls: maturity 0.5, Draft. Hardware design description and isolation diagram drafted against the approved architecture, with schematics under way.
- Hardware & Chip Design and Implementation: maturity 0.8, Feature complete. Board designs released under design control with the hardware design description complete; engineering builds and bench tests follow.^A
Device software (IEC 62304)^D
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Software requirements drafted from the design inputs, with software of unknown provenance and development tools identified.
- System, Chip & Software Architecture with Risk Controls: maturity 0.5, Draft. Software requirements and architecture approved with the safety class confirmed, and units and integration builds under way.
- Hardware & Chip Design and Implementation: maturity 0.5, Draft. Software requirements and architecture approved with the safety class confirmed, and units and integration builds under way.
Product cybersecurity^A
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Initial threat model and security requirements drafted with the design inputs, from the intended use and the use environments.
- System, Chip & Software Architecture with Risk Controls: maturity 0.5, Draft. Threat model and security architecture approved, with secure boot, update and access controls being built.
- Hardware & Chip Design and Implementation: maturity 0.5, Draft. Threat model and security architecture approved, with secure boot, update and access controls being built.
Electrical safety, EMC and compliance testing^A
- Design Inputs & Hazard Analysis: maturity 0.0, Planned. Electrical safety and EMC test plan started from the applicable standards list, with the test laboratory route chosen.
- System, Chip & Software Architecture with Risk Controls: maturity 0.3, Early draft. Test plan mapped to the architecture's means of protection, isolation and essential performance.
- Hardware & Chip Design and Implementation: maturity 0.5, Draft. Pre-compliance checks run on early hardware, with the laboratory booked.
Usability engineering and design validation^A
- Design Inputs & Hazard Analysis: maturity 0.3, Early draft. Use specification approved with the users, use environments and user interface characteristics, and the use-related risk analysis started.
- System, Chip & Software Architecture with Risk Controls: maturity 0.5, Draft. User interface specification approved, with formative evaluations running on prototypes.
- Hardware & Chip Design and Implementation: maturity 0.5, Draft. User interface specification approved, with formative evaluations running on prototypes.
Manufacturing, test and supply^A
- System, Chip & Software Architecture with Risk Controls: maturity 0.0, Planned. Critical parts and suppliers listed from the chip specification and the architecture, with an initial approved supplier list.
- Hardware & Chip Design and Implementation: maturity 0.3, Early draft. Suppliers, foundry and assembly partners being qualified, with quality agreements and change notification terms drafted.

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