Uses approximately timed models and traffic generators to compare architecture options, such as interconnect topology, memory controller settings, cache sizes or where to place an accelerator, before the choice is fixed in RTL.
This sub-function's own lane. See it beside the other sub-functions of system modelling and virtual prototyping on the function's swimlane.
Chevrons show maturity by the end of each stage and open that stage's row below; diamonds are freeze and sign-off points; triangles are the lifecycle's gates.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.