Chip lifecycle / Functions / Performance and power-performance analysis / Power estimation at architecture and RTL

Power estimation at architecture and RTL

Estimates dynamic and leakage power early from activity models, then at RTL from simulation or emulation activity, so power targets are tracked alongside performance and power management choices are made with data.

Across the lifecycle

This sub-function's own lane. See it beside the other sub-functions of performance and power-performance analysis on the function's swimlane.

In the SoC lifecycle

Chevrons show maturity by the end of each stage and open that stage's row below; diamonds are freeze and sign-off points; triangles are the lifecycle's gates.

Stage

01 Concept & Feasibility

02 SoC Specification & Architecture

03 IP Integration

04 SoC RTL Design

05 Full-Chip Verification

06 Full-Chip DFT

07 Physical Design & Sign-off

08 Tape-out

09 Foundry & Mask

10 Packaging & Test

11 Bring-up & Silicon Validation

12 Qualification & Reliability

13 Production Ramp & Yield

14 Volume Production & Sustaining

15 End of Life

Product milestones

CAConcept approval PPProduct plan agreed ESEngineering samples PRProduction release VRVolume ramp LTBLast-time buy EOLLast-time ship

Chip milestones

TFTR1TR1: Technology feasibility SFSpecification freeze IICIP integration complete RFRTL freeze VSVerification sign-off DSDFT insertion sign-off PSPhysical sign-off TTRTR2TR2: Tape-out technology readiness TOTape-out FSFirst silicon FPTFirst packaged parts tested SVSilicon validated QSQualification start QPTR3Qualification passed DADesign and test data archived

Power estimation at architecture and RTL^A

1.0

Key0.0Started0.3Early draft0.5In progress0.8Feature complete1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.AI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

Show this chart as a list

Stages

Product milestones

Chip milestones

TR1: Technology feasibility (TF) (technical readiness review TR1)
Specification freeze (SF)
IP integration complete (IIC)
RTL freeze (RF)
Verification sign-off (VS)
DFT insertion sign-off (DS)
Physical sign-off (PS)
TR2: Tape-out technology readiness (TTR) (technical readiness review TR2)
Tape-out (TO)
First silicon (FS)
First packaged parts tested (FPT)
Silicon validated (SV)
Qualification start (QS)
Qualification passed (QP) (technical readiness review TR3)
Design and test data archived (DA)

Sub-functions

Power estimation at architecture and RTL^A
- SoC Specification & Architecture: maturity 0.0, Started
- SoC RTL Design: maturity 0.5, In progress
- Full-Chip Verification: maturity 0.8, Feature complete
- Physical Design & Sign-off: maturity 1.0, Complete; Power estimates final (feeds a gate)
- Bring-up & Silicon Validation: maturity Freeze, Frozen; Power correlated with silicon (feeds a gate)

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