Bringing each block's timing constraints, power intent and test structures into the chip's own and checking they fit.
This sub-function's own lane. See it beside the other sub-functions of ip integration on the function's swimlane.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.
Chevrons show maturity by the end of each stage and open that stage's row below; diamonds are freeze and sign-off points; triangles are the lifecycle's gates.