Chip lifecycle / Checklists / Test program lifecycle / Test Strategy & DFT Alignment: exit checklist

Test Strategy & DFT Alignment: exit checklist

Before the DFT architecture aligned gate, the test engineering manager and the DFT architect confirm the test strategy, cost model and DFT architecture are complete, agreed by design and test, and traceable.

1. Test strategy and cost

MustThe outgoing quality target is stated per market, with its source named.
Evidence
Outgoing quality target
Owner
Product engineer
MustThe cost of test budget is stated and linked to the business case.
Evidence
Test cost model
Owner
Test cost and capacity engineer
MustEvery expected defect type has a screen and an insertion.
Evidence
Test strategy
Owner
Product engineer
SeeDecision: Wafer sort and final test split
ShouldThe cost model shows its sensitivities to test time, yield, site count and tester class.
Evidence
Test cost model
Owner
Test cost and capacity engineer

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