Moves the team into tile circuit design and device RTL assembly once the configuration and security architecture is frozen, with the verification environment built alongside. The circuit design lead and the verification lead run it together.
MustThe fabric, configuration and hard IP integration specifications are frozen and available.
MustThe PDK, transistor models and layout rules are at the versions agreed for tile design.
SeeDecision: PDK and library version lockFlow: Moving PDK or tool versions mid-project
MustTile boundary and abutment rules are agreed between the tile and physical design teams.
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