Moves the team into regressions and coverage closure on the frozen tiles and device RTL once the tile and RTL freeze is held. The verification lead runs it with the circuit design lead.
MustThe tiles, the fabric RTL and the netlists are frozen at the tile and RTL freeze, at stated versions.
MustThe verification environment runs on the frozen RTL, with the plan final and the coverage model complete.
SeeWork product: Verification planDecision: Verification methodology and configured design simulation
MustAn early bitstream generator build can write bitstreams from test designs for configured design simulation.
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