Chip lifecycle / Checklists / FPGA lifecycle / System Validation & Compliance: exit checklist

System Validation & Compliance: exit checklist

Use before the system validated gate. Run by the hardware validation engineer.

1. Validation

MustThe system test plan has been executed and results reviewed.
Evidence
System test report
Owner
Hardware validation engineer
MustTests across the temperature and supply range of the product are done.
Evidence
System test report
Owner
Hardware validation engineer
SeeDecision: Speed grade, temperature grade and package
MustKnown issues are documented with impact and planned fix.
Evidence
Known issues list
Owner
Hardware validation engineer
SeeFlow: Silicon errata: found, classified, published and tracked

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