1. Purpose of the gate
Silicon correlated closes the engineering part of the Silicon Characterisation stage on the circuit track. It confirms that the team understands its silicon: every specification target has been measured under the planned conditions, every significant difference from simulation has a cause, and the trim and calibration settings that production will apply are known. The Correlation complete marker is recorded here.
Correlation matters beyond the current product. The device models, extraction set-up and design methods that produced this circuit will be used for the next one in the same process. A difference left unexplained here is likely to repeat, and a model error left uncorrected becomes a design error later. For a block inside a SoC, the results also tell the SoC team whether the block behaves as its models said.
The criteria are that measured performance is compared with every specification target, model to silicon differences are explained, and trim and calibration settings are derived. On the product lifecycle, this gate feeds the product's engineering samples.
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