1. Purpose of the gate
Post-layout sign-off closes the Post-Layout Verification & Sign-off stage and is the technical release of the block. After it, the layout is released and only the release activities of the next stage remain. It confirms both that performance survives the layout and that the block is physically safe and reliable.
The gate is where problems found too late become expensive. A performance shortfall here means layout rework; one found on silicon means a respin. The review therefore looks hard at the differences between pre-layout and post-layout results, not only at whether the post-layout results pass.
The criteria are that post-layout performance is within specification or waived, electromigration and IR drop are within the process rules, and ESD and latch-up checks pass.
10 more sections for registered members.