1. Purpose and scope
This stage proves that the circuit meets its specification across the full range of conditions it will meet in use, and that it works with the digital logic around it. It runs from the Schematic design review to the Pre-layout verification complete gate. The Schematic released to layout and Behavioural models validated milestones fall within it.
Analog verification has two parts. The first is performance verification: simulating every target across process, voltage and temperature corners and across statistical variation, so that the circuit meets its limits not only at nominal conditions but on parts at the edges of the manufacturing spread. The second is functional and integration verification: checking that modes, control bits, calibration, power sequencing and digital interfaces behave correctly together, usually with behavioural models in a mixed-signal simulation of the larger chip.
The stage is where many analog problems are found, and where the cost of finding them is still modest. Problems found here are fixed in schematics; the same problems found after layout cost layout rework, and found on silicon cost a new mask set or a respin of the SoC.
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