Designing how many accelerators work as one: the links between chips and between servers, the topology, the collective communication the software uses, and a reference design for racks and clusters. Scale-out design also runs alongside chip design from the architecture onwards; this stage holds the release of the cluster reference design.
This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.