STA Physical Design Engineer, Senior Principal

Independently drive PnR activities from RTL to GDS, ensuring robust signoff across complex SoCs or sub-systems. Identify RTL issues early and work with frontend team on resolution. Hands-on experience with various custom clocking techniques. Experience with high-speed designs with serdes/ddr IPs. Good understanding of PnR tool and signoff flows like Extraction, STA, Formality, EM-IR and DRC/LVS etc