Acronym · Interfaces & SerDes
SPI (Serial Peripheral Interface)
A simple four-wire full-duplex master-driven bus with separate clock, data in, data out and chip select lines. It has no formal standard, so timing modes and framing vary between devices.
- Type
- Acronym
- Domain
- Interfaces & SerDes, Peripheral and embedded bus
Notes
The absence of a governing specification is why SPI clock polarity and phase modes must be checked device by device.
Overview
SPI, short for Serial Peripheral Interface, is a simple synchronous serial bus in which one controller drives a clock and exchanges data with peripheral chips over separate data-out and data-in lines, selecting each peripheral with its own chip select line. It is one of the most common ways for a microcontroller or SoC to talk to flash memory, sensors, displays, data converters and other nearby chips on a board. SPI began at Motorola and has never been formally standardised, so details vary from one device to another.
How it works
A basic SPI link uses four signals: a clock driven by the controller, a controller-to-peripheral data line (traditionally MOSI, now often COPI), a peripheral-to-controller line (MISO or CIPO) and a chip select, usually active low. The controller pulls one chip select low and toggles the clock, and on each clock one bit shifts out in each direction, so transfers can be full duplex. There are no addresses and no acknowledgements, so the controller may not even know whether a peripheral is present.
Clock polarity (CPOL) and clock phase (CPHA) combine into four modes that set the idle clock level and the edge on which data is sampled; controller and peripheral must agree, and modes 0 and 3 are the most common. Clock rates are often around 10 MHz. Each extra peripheral normally needs its own chip select line, although some devices can be daisy-chained so that their shift registers form one long chain.
Variants trade the classic form for speed or pin count. A three-wire form shares one data line in half duplex, and dual and quad SPI use two or four data lines per clock, which is popular for flash memory that must deliver large amounts of data, such as boot images. Compared with I2C, SPI is faster and needs no pull-up resistors, but it uses more pins and has no built-in error checking or flow control.
Examples
- A microcontroller reading an accelerometer over SPI in mode 0.
- An SoC booting from a quad SPI NOR flash chip, using four data lines to read its boot image faster.
- Several data converters daisy-chained so that one chip select line reads them all as a single long shift register.
- A Linux devicetree entry declaring an SPI device, its chip select and maximum clock rate, because SPI devices cannot be discovered automatically.
Why it matters
Peripheral IP designers build SPI controllers, board designers route the signals, and firmware and driver engineers configure modes and timing for each device. Because there is no formal standard, each device's mode and timing must be checked against its datasheet, and many SoCs boot from SPI or quad SPI flash.
In the chip lifecycle, SPI controllers are chosen at architecture and verified in RTL against models of target devices, boot flash support is fixed in the boot ROM at tapeout, and SPI links are among the first interfaces exercised during board bring-up.
It matters most to: Bare-Metal MCU Software Engineer, Embedded Software Engineer, Hardware Design Engineer (Board Level), Microcontroller and Embedded Processor FAE, Peripheral and Bus IP Design Engineer
Common confusions
- Not the same as I2C
- I2C uses two shared wires with device addresses and acknowledgements, and is slower. SPI uses more wires and a chip select per device, and gives higher throughput with less protocol. SPI vs I2C
- Not the same as QSPI
- Quad SPI keeps the SPI clock and chip select but uses four data lines together in one direction at a time, mainly for flash memory. It is an extension of SPI, not a separate bus.
- Not the same as solder paste inspection
- In circuit board assembly, SPI also means solder paste inspection, the optical check of solder paste deposits before components are placed.
Sources
- Overview of Linux kernel SPI support (opens in a new tab), The Linux Kernel documentation (kernel.org), 2026-10-22
- SPI Background (opens in a new tab), Total Phase, 2026-10-22
- Serial Peripheral Interface (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
Related terms
Part of the Interfaces & SerDes glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 18 pages of the Hub. In each group, the pages that mention it most come first.
Skills
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary