Acronym · Interfaces & SerDes
I2C (Inter Integrated Circuit)
A two-wire bus with addressed devices, open-drain and bidirectional at speeds from 100 kbps to 3.4 Mbps, with a one-way, push-pull Ultra Fast-mode at up to 5 Mbps, used everywhere for configuration, sensors, EEPROMs and power management control.
- Also known as
- IIC, I2C bus, TWI
- Type
- Acronym
- Domain
- Interfaces & SerDes, Peripheral and embedded bus
Notes
Created by Philips in 1982; the name Two Wire Interface exists mainly because of the former trademark on I2C.
Overview
I2C (Inter-Integrated Circuit) is a two-wire serial bus, first developed by Philips Semiconductors, that lets a controller communicate with many low-speed devices using just a data line and a clock line. It is the usual way to configure chips and to read sensors, small memories, data converters and power management parts on a board. Each device on the bus has its own address, so many parts can share the same two wires.
How it works
The two lines, SDA for data and SCL for clock, are open-drain: a device can only pull a line low, and pull-up resistors bring it back high. Because any device pulling low wins, the bus behaves as a wired-AND and two drivers can never fight destructively. A controller claims the bus with a START condition, sends a 7-bit target address and a read or write bit, and waits for the target to acknowledge. Data then moves in bytes, each followed by an acknowledge bit, and a STOP condition releases the bus. A rarely used 10-bit address format also exists.
The specification defines several speeds: up to 100 kbit/s in Standard-mode, 400 kbit/s in Fast-mode, 1 Mbit/s in Fast-mode Plus and 3.4 Mbit/s in High-speed mode, plus a one-way Ultra Fast-mode at up to 5 Mbit/s. Since the lines rise through resistors, bus capacitance limits both speed and the number of devices: a smaller pull-up gives faster edges but costs more power.
I2C supports more than one controller, with arbitration and clock synchronisation sorting out simultaneous starts, and a target can hold the clock low to stretch a transfer. SMBus and PMBus build on it for system and power management. NXP's 2021 revision renamed master and slave to controller and target, in line with MIPI I3C, the faster successor that can share a bus with legacy I2C devices.
Examples
- A processor configuring an audio codec or camera module by writing its registers over I2C.
- The TI ADS1115 converter, which returns 16-bit conversion results to a host over I2C.
- A power management IC reporting voltages and temperatures over SMBus or PMBus, which are built on I2C.
- A small serial EEPROM that stores a board's identity and calibration data and is read at start-up.
- A mixed bus where newer MIPI I3C devices share the two wires with legacy I2C parts.
Why it matters
I2C is described by NXP as a de facto world standard and appears on most SoCs, microcontrollers and boards, so peripheral IP designers, board designers, firmware engineers and bring-up engineers all work with it. It is often among the first interfaces used on new hardware, and pull-up sizing, address clashes and mismatched voltage levels are typical things to check.
In the chip lifecycle, I2C is chosen at architecture as a control bus, integrated as controller or target IP during design, checked with bus models in verification, and exercised heavily during board bring-up, production test configuration and in the field.
It matters most to: Board Bring-up Engineer, Embedded / Firmware Engineer, Firmware Engineer, Hardware Design Engineer (Board Level), Peripheral and Bus IP Design Engineer
Common confusions
- Not the same as SPI
- SPI uses separate data lines in each direction, a clock and usually a select line per device. It runs faster but needs more pins, while I2C shares two wires and selects devices by address. I2C vs SPI
- Not the same as I3C
- MIPI I3C is a newer two-wire bus with much higher data rates, in-band interrupts and dynamic addressing. It can share a bus with I2C devices but is a separate specification.
- Not the same as SMBus
- SMBus is a stricter derivative of I2C with its own specification for timing, electrical levels and commands, aimed at system management. Many devices support both.
Related standards
- MIPI I3C (two-wire successor bus that is backward compatible with I2C devices)
Sources
- UM10204: I2C-bus specification and user manual, Rev. 7.0 (1 October 2021) (opens in a new tab), NXP Semiconductors, 2026-10-22
- A Basic Guide to I2C, SBAA565 (Joseph Wu, November 2022) (opens in a new tab), Texas Instruments, 2026-10-22
- MIPI I3C and I3C Basic (opens in a new tab), MIPI Alliance, 2026-10-22
- ADS1115: 16-bit, 860-SPS, 4-channel, delta-sigma ADC with PGA, oscillator, VREF, comparator and I2C (opens in a new tab), Texas Instruments, 2026-10-22
- I2C (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
Related terms
Part of the Interfaces & SerDes glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 14 pages of the Hub. In each group, the pages that mention it most come first.
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