Silicon interposer

Notes

Limited by the lithography reticle field, which is why stitched and multi-reticle interposers became a scaling issue for large AI packages.

Overview

A silicon interposer is a slab of silicon carrying fine metal wiring and through-silicon vias, on which several dies, such as a processor and stacks of high-bandwidth memory, are mounted side by side and wired together before the assembly goes onto a package substrate. It is the defining part of 2.5D packaging, giving connections between dies far denser than an organic substrate can offer. Most silicon interposers are passive, containing wiring and sometimes capacitors but no transistors.

How it works

An interposer is made in a wafer fab with CMOS-style processing, but at relaxed dimensions: Semiconductor Engineering reports that interposers are often built on older processes and lithography wavelengths such as 248 nm or even 365 nm, which keeps cost down. Several layers of fine copper wiring connect bumps under one die to bumps under another, and through-silicon vias, etched deep into the substrate with a process closer to MEMS deep etching than to standard CMOS, carry power and signals down to the package substrate. TSMC's CoWoS-S interposers also embed deep trench capacitors to steady the power supply.

Dies are bonded on top while the interposer is still in wafer form, and the resulting module is then attached to an organic package substrate; TSMC describes this as chip on wafer bonding followed by attachment to the substrate.

The main limit is size. A single lithography exposure covers one reticle field, but interposers that host a large processor and several memory stacks are bigger than that, so their layers must be stitched from several overlapping exposures. That works, but it cuts throughput and adds cost and design restrictions at the stitch boundaries. TSMC's CoWoS-S reaches about 3.3 times the reticle size; beyond that, alternatives use organic redistribution-layer interposers or small silicon bridges embedded only where dense links are needed.

Examples

• TSMC's CoWoS-S, which places logic dies and HBM stacks on a silicon interposer of up to about 3.3 times the reticle size.
• A three-reticle interposer whose wiring layers each need three stitched exposures.
• Embedded deep trench capacitors built into an interposer to improve power delivery to the dies above.
• TSMC's 2012 CoWoS test vehicle joining a logic SoC and Wide I/O DRAM on one interposer.

Why it matters

Silicon interposers made today's AI accelerators with on-package high-bandwidth memory practical, because thousands of memory connections need wiring far finer than a laminate substrate. Interposer designers, 2.5D integration engineers, signal and power integrity specialists and foundry packaging teams work on them, and interposer capacity and cost can constrain how many such products can be built.

Related terms

• 2.5D integration
• CoWoS
• TSV
• Organic interposer

Where it appears on the Hub

Used on 6 pages of the Hub. In each group, the pages that mention it most come first.