Artefact · Compute & AI Hardware
Performance model
A model that predicts how fast and how efficiently a chip design will run its target workloads, built from analysis or simulation before the design is fixed and kept in step with it.
- Also known as
- Performance modelling, Architecture performance model
- Type
- Artefact
- Domain
- Compute & AI Hardware, AI acceleration
Overview
A performance model estimates the throughput, latency and energy of a design on chosen workloads without building the hardware. Architects use it to compare candidate designs, set performance targets and check that the finished design and silicon behave as planned.

How it works
The simplest models are analytical: they count the operations and data movement a workload needs and divide by the compute and bandwidth a design offers, as a roofline model does. More detailed models simulate the design at the level of its compute units, memories and interconnect, sometimes cycle by cycle, while running traces of real workloads.
The model is built before the architecture is frozen and explored together with the software team, because the same hardware can perform very differently depending on how the compiler maps work onto it. Each choice of compute, memory, interconnect and number format is tried in the model first.
Later the model becomes a reference: performance verification compares the design code against it, and measurements on silicon are compared with it to find where the design or the software falls short. The model is then corrected so the next design starts from better data.
Examples
- Estimating whether a candidate accelerator meets an inference latency target on a set of models.
- Comparing two on-chip memory sizes by the bandwidth each saves on the target workloads.
- Checking a processor design's expected instructions per cycle on standard benchmark traces.
- Correlating benchmark results on first silicon with the model's predictions.
Why it matters
A design that looks fast on paper can be limited by memory bandwidth, communication or software. The performance model is where those limits are found while the design can still change. It is owned by performance modelling engineers and used by architects, compiler teams and product managers from the first workload analysis to benchmarking on silicon.
It matters most to: AI Systems Performance Architect, ML Compiler Engineer, NPU / AI Accelerator Architect, Performance Modeling Engineer
Common confusions
- Not the same as Roofline model
- A roofline model is one simple kind of analytical performance model that bounds performance by compute or bandwidth; a full performance model may simulate the design in much more detail.
- Not the same as Virtual prototype
- A virtual prototype runs software on a functional model of the hardware so software can start early; a performance model predicts speed and efficiency and may not run real software at all.
Sources
- Roofline: An Insightful Visual Performance Model for Floating-Point Programs and Multicore Architectures (UCB/EECS-2008-134) (opens in a new tab), University of California, Berkeley, EECS Department, 2026-11-10
- gem5: The gem5 simulator system (opens in a new tab), gem5 project, 2026-11-10
- Roofline model (opens in a new tab), Wikipedia, 2026-11-10
Related terms
Part of the Compute & AI Hardware glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 21 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
- Performance Modelling & Co-design (AI accelerator lifecycle)
- Performance targets baselined (AI accelerator lifecycle)
- Architecture freeze (AI accelerator lifecycle)
- Architecture & Microarchitecture (AI accelerator lifecycle)
- Benchmarking & Performance Tuning (AI accelerator lifecycle)
- RTL Design & Verification (AI accelerator lifecycle)
- and 2 more
Roles
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary