Tool · Verification & Validation
Palladium
Cadence's hardware emulation platform, built on custom processor-based emulation chips rather than commercial FPGAs. It is one of the three emulators that dominate large SoC verification projects.
- Also known as
- Palladium Z2, Palladium Z3
- Type
- Tool
- Domain
- Verification & Validation, Emulation & prototyping
Notes
Processor-based architecture gives fast compile times and deep visibility compared with FPGA-based emulators.
Overview
Palladium is Cadence's family of hardware emulation systems, which run a chip's RTL on dedicated hardware so it can be verified and debugged far faster than in a software simulator. It is built on Cadence's own custom emulation silicon rather than commercial FPGAs, and is used to verify large SoCs, run real software before chips exist and analyse power. The current generation, Palladium Z3, was announced in April 2024 alongside the Protium X3 FPGA prototyping system.
How it works
The RTL is compiled onto the emulator, partitioned across many chips and boards, and then run cycle by cycle while keeping internal signals visible for debug. Cadence says its modular compiler allows about three compile turns a day for billion-gate designs, and debug triggers run at speed without recompiling. The design can be driven by a testbench on a host computer, combined with virtual models of the rest of the system, or connected to real hardware through in-circuit emulation ports.
Palladium Z3 scales to 48 billion gates, and Cadence quotes 1.5 times the performance of Palladium Z2 and more than double the capacity of the previous generation. It shares a front end and interfaces with Protium, so a design can move from emulation to prototyping. Apps add four-state emulation for X-propagation and switched power domains, real number modelling for mixed-signal designs, dynamic power analysis across billions of gates and fault emulation for ISO 26262 safety work. A smaller, air-cooled System Studio version starts at 128 million gates.
Emulators are a significant investment and are shared between teams, so Cadence also offers a job scheduling app for queueing work. Emulation does not replace simulation everywhere: some checks need dedicated modes, and analogue blocks must be modelled rather than simulated in detail.
Examples
- Booting an operating system on an emulated SoC in Palladium Z3 to find hardware and software integration bugs before tapeout.
- Dynamic power analysis of real software workloads on a multi-billion-gate design using the Palladium Dynamic Power Analysis App.
- Serial fault emulation with the Palladium Safety App to support an ISO 26262 safety campaign.
- Moving a verified design from Palladium Z3 to Protium X3 for faster software validation through their shared front end.
- Third-party debuggers such as Lauterbach Trace32 connecting to emulated processor cores over JTAG.
Why it matters
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