Mixed-signal simulation

Notes

Interface element configuration, rather than the solvers themselves, is usually where mixed-signal setups go wrong.

Overview

Mixed-signal simulation is the simulation of a design containing both analogue and digital circuits in a single run, coupling a continuous-time circuit solver for the analogue parts with an event-driven logic simulator for the digital parts. It lets engineers verify blocks such as data converters, PLLs, power management and sensor interfaces working together with the digital logic that controls them. It sits between transistor-level SPICE simulation, which is accurate but slow, and digital simulation, which is fast but cannot represent voltages and currents.

How it works

The design is split into analogue and digital partitions. Analogue parts are described as transistor-level netlists or as behavioural models in languages such as Verilog-A or Verilog-AMS, and solved by a SPICE or FastSPICE engine that computes voltages and currents over time. Digital parts, written in Verilog, SystemVerilog or VHDL, run on an event-driven logic simulator. Where a signal crosses the boundary, interface elements turn a logic transition into a voltage waveform, or a voltage crossing a threshold into a logic event, so analogue events can trigger digital actions and the reverse.

Teams choose the level of detail block by block. Transistor-level analogue is the most accurate and the slowest. Behavioural models, and real number models that pass analogue values as numbers inside the digital simulator, run much faster and allow long regressions with digital methods such as UVM, coverage and assertions. Flows can be analogue-centric, driven from the circuit design environment, or digital-centric, driven from the logic verification environment.

The hard part is the boundary. Errors in mixed-signal designs most often occur at the interfaces between analogue and digital blocks, and some appear only higher in the hierarchy, sometimes at the chip's pins. Behavioural models are only useful if they are checked against the circuits they stand in for.

Examples

• An ADC simulated at transistor level together with the RTL of its digital calibration logic.
• A PLL lock sequence checked using a behavioural oscillator model alongside the digital lock detector and control registers.
• A power management start-up sequence verified with real number models inside a UVM testbench.
• Siemens Symphony combining the Analog FastSPICE engine with the Questa logic simulator.
• Cadence Spectre AMS Designer running with the Xcelium logic simulator for full SoC mixed-signal verification.

Related terms

• Verilog-A
• FastSPICE
• Spectre
• SPICE deck

Where it appears on the Hub

Used on 18 pages of the Hub. In each group, the pages that mention it most come first.