Standard · Interfaces & SerDes
MIPI M-PHY
A MIPI embedded-clock serial physical layer with multiple gear speeds and power states, designed for chip-to-chip links that must idle at very low power, and used underneath UFS and UniPro.
- Also known as
- M-PHY
- Type
- Standard
- Domain
- Interfaces & SerDes, Peripheral and embedded bus
Notes
Its HS-GEAR ladder is how UFS advertises successive speed generations without changing the protocol layer.
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