Standard · Interfaces & SerDes
MIPI C-PHY
A MIPI physical layer that sends three-wire trios with embedded clock, encoding 16 bits per seven symbols. It achieves more bits per wire than D-PHY at the same toggle rate, saving pins.
- Also known as
- C-PHY
- Type
- Standard
- Domain
- Interfaces & SerDes, Display and imaging interface
Notes
Its three-level trio signalling makes board routing and EMI behaviour noticeably different from differential pairs.
Related terms
- MIPI D-PHY
- MIPI CSI-2
- MIPI DSI
- Embedded clock
Part of the Interfaces & SerDes glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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