Link training

Notes

Training time became a system-level concern with PCIe Gen5 and Gen6 because boot and hot-plug budgets assume links come up in milliseconds.

Overview

Link training is the start-up procedure in which the two ends of a high-speed serial link exchange known patterns and control messages to tune their transmitters and receivers, line up their lanes and agree how fast and how wide the link will run. It runs automatically whenever the link comes up, and again when errors force a retrain. Without it, a multi-gigabit link would depend on fixed settings that suit no real channel well.

How it works

In PCI Express, a state machine in each port, the LTSSM, steps through the process. The partners first detect each other, then exchange repeated training sequences so that their receivers can lock on to the incoming signal and negotiate link parameters. They agree the link width, choosing the widest lane count both support, and the receivers compensate for skew between lanes so that data striped across them can be reassembled. Links start at the lowest data rate and move up once both ends are ready.

At higher rates, training includes equalisation. In PCIe 3.0, the link first runs at 2.5 GT/s while the upstream port passes the downstream device a starting transmitter preset; after the change to 8 GT/s, each side in turn adjusts its partner's transmit equaliser while tuning its own receiver, until both reach a low error rate.

Ethernet backplane PHYs such as 10GBASE-KR do something similar. Each side sends training frames that begin with a frame marker, carry a low-rate control channel and end with a pseudo-random training pattern. Through the control channel, a receiver asks the far transmitter to increment, decrement or hold each equaliser tap, or to jump to a preset or initial state, and reports status until it declares itself ready. Die-to-die links such as UCIe include training logic in their physical layer too.

Examples

• A PCIe 3.0 link that starts at 2.5 GT/s, exchanges a transmitter preset, and runs the equalisation phases before settling at 8 GT/s.
• A graphics card that comes up as a narrower link than its slot allows because some lanes fail to train.
• A 10GBASE-KR backplane port exchanging coefficient update requests with its partner until the receiver reports that training is complete.
• A UCIe die-to-die PHY that uses its sideband channel to exchange parameters during initialisation and training.

Why it matters

SerDes PHY designers build the adaptation circuits, controller designers implement the training state machines, firmware engineers tune presets and retry behaviour, and validation engineers check that links train reliably across many channels, temperatures and supply voltages. A link that trains narrower or slower than expected loses performance silently.

Related terms

• FFE
• PCIe
• Equalisation
• Ethernet

Where it appears on the Hub

Used on 13 pages of the Hub. In each group, the pages that mention it most come first.