HCI (Hot Carrier Injection)

Notes

Because it is aggravated by cold, HCI is the mechanism that low temperature operating life testing is designed to accelerate.

Overview

Hot carrier injection (HCI) is a transistor wear-out mechanism in which charge carriers, accelerated by the strong electric field near the drain, gain enough energy to enter the gate dielectric or damage its interface with the channel. The trapped charge and interface damage build up slowly, shifting the threshold voltage and reducing drive current, so circuits gradually slow down or drift out of specification. HCI is one of the front-end ageing mechanisms, alongside bias temperature instability and time-dependent dielectric breakdown, that reliability engineers characterise and model for every process.

How it works

When a MOSFET conducts with a high drain voltage, the lateral field peaks at the drain end of the channel. Some carriers gain enough energy there to cause impact ionisation, seen as substrate current, and a small fraction are injected into the gate dielectric, where they are trapped or break bonds at the silicon interface. Threshold voltage, transconductance and saturation current then drift. Because the damage needs current at high drain bias, it builds up mainly during switching transitions in logic and in analogue transistors biased in saturation.

N-channel devices have traditionally been the more affected type. Classic HCI tends to get worse at low temperature, because reduced phonon scattering lets carriers reach higher energies, which matters for chips that run cold. In FinFETs and new channel materials the picture is more complex: Semiconductor Engineering reports that self-heating and fin geometry affect HCI, and that some SiGe channel choices that reduce NBTI can make HCI worse.

Process engineers measure HCI on test transistors under accelerated DC stress and extrapolate the drift to lifetime at use conditions. JEDEC publishes separate procedures for n-channel and p-channel devices so that results can be compared between technologies. Designers then simulate with ageing models from the design kit and keep timing or bias margin.

Examples

• A foundry stressing n-channel test transistors at raised drain voltage and reporting parameter shift using the JESD28 procedure.
• A reliability lab characterising p-channel hot-carrier degradation at the gate voltage that gives maximum gate current, as JESD60 describes.
• A cryogenic control chip whose designers allow extra margin because hot-carrier damage is worse at low temperature.
• Ageing-aware timing analysis that adds margin to paths whose transistors switch often at high drain bias.
• A reliability engineer combining HCI, BTI and TDDB contributions into one failure rate using the sum-of-failure-rates method in JEP122.

Related terms

• NBTI
• LTOL
• TDDB
• BTI

Where it appears on the Hub

Used on 6 pages of the Hub. In each group, the pages that mention it most come first.