FPGA-to-ASIC conversion

Overview

FPGA-to-ASIC conversion is the route from a programmable part to a fixed one. A design is first built and proven on an FPGA, where it can be changed easily. When the function has settled and the volume is high enough, the same design is moved onto a chip made for it, which costs less per unit and uses less power but can no longer be reprogrammed.

How it works

The conversion starts from the FPGA design's code, constraints and test environment. FPGA-specific parts, such as vendor memory blocks, clock managers and transceivers, are mapped to equivalent blocks on the target chip. Timing is closed again for the new technology, and test logic for manufacturing test is added, since an FPGA design usually has none.

The converted design is checked against the FPGA version, often by running the same tests and by formal equivalence checks where possible. The target is often a structured ASIC, where only a few custom layers are made, which keeps cost and turnaround lower than a full standard cell chip. Pin-compatible targets let the customer keep the same board.

The customer pays one-time engineering and mask charges, so the decision rests on volume, the expected unit saving and how stable the design is.

Examples

• A communications design converted from an FPGA to a structured ASIC once its volume justifies the custom masks.
• An industrial controller converted to a pin-compatible fixed chip so the board stays the same.
• A conversion where FPGA memory blocks are replaced by compiled memories on the target chip.
• A design kept on the FPGA because its protocol was still changing.

Why it matters

FPGAs let products reach the market quickly, but their unit cost and power can be too high at volume. Conversion lets a company keep the time-to-market benefit of the FPGA and then lower its costs later. FPGA designers, conversion engineers, ASIC design service teams and product managers are involved.

In the structured ASIC lifecycle, conversion is often how a customer design arrives: the FPGA design is the starting point for design intake.

It matters most to: ASIC Design Engineer (Structured and Custom Digital), ASIC Vendor Engineering Manager, FPGA Design Engineer, FPGA-to-ASIC Conversion Engineer

Common confusions

Not the same as a structured ASIC

A structured ASIC is a kind of chip. FPGA-to-ASIC conversion is a route a design takes, and its target may be a structured ASIC or a standard cell ASIC.

Not the same as FPGA prototyping

FPGA prototyping uses FPGAs to test a chip design before it is made. In conversion the FPGA design came first and was itself the product.

Sources

1. A Methodology for FPGA to Structured-ASIC Synthesis and Verification (DATE 2006) (opens in a new tab), Design, Automation and Test in Europe (DATE) proceedings archive, 2026-11-10
2. Measuring and Navigating the Gap Between FPGAs and ASICs (PhD thesis, Ian Kuon, 2007) (opens in a new tab), University of Toronto, 2026-11-10
3. Structured ASIC platform (opens in a new tab), Wikipedia, 2026-11-10

Related terms

• FPGA
• Structured ASIC
• ASIC
• NRE

Where it appears on the Hub

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