Defect review

Notes

Only a sample of detected defects is reviewed, so review sampling strategy strongly shapes what engineers believe is happening.

Overview

Defect review is the fab step in which sites flagged by a wafer inspection tool are revisited at high magnification, usually with a scanning electron microscope, so that each defect can be imaged, classified and judged for its likely cause and effect on yield. Inspection finds where something looks wrong; review shows what it actually is. Because review is slow compared with inspection, fabs review a chosen sample of the flagged sites rather than all of them.

How it works

An optical or e-beam inspection tool scans the wafer and writes a list of defect coordinates. The review tool, typically a dedicated review SEM, loads the wafer, aligns to it, drives to each selected coordinate, relocates the defect and captures high-resolution images. Some review tools can also analyse a defect's composition with energy-dispersive X-ray spectroscopy, which helps show what a particle is made of.

Each reviewed defect is given a class, such as particle, bridge, break, line collapse or residue, or marked as a nuisance that does not matter. Automatic defect classification now does much of this work, increasingly with machine learning models trained on labelled images. The results are summarised as a Pareto chart of defect types for each layer, which engineers use to decide which problems to attack first.

Two practical limits shape the work. The first is sampling: a wafer may carry far more flagged sites than can be reviewed, so engineers pick samples, for example a fixed random number per layer, or targeted samples aimed at defect types of interest. The second is visibility: very small defects may not show up in the SEM image at all, and a high share of these 'not found' or SEM non-visual results distorts the Pareto. Linking the review tool to the optical images taken by the inspector helps reduce them.

Examples

• Reviewing a random sample of 100 defects from one wafer per layer to build a layer-by-layer defect Pareto during EUV process development.
• A deep learning classifier sorting SEM review images of line and space patterns into bridges, breaks and line collapse.
• Energy-dispersive X-ray analysis on a review SEM used to classify small defects by their composition.
• Feeding the inspector's optical patch images to the review SEM to cut the number of defects reported as not found.
• SEM review separating missing vias from nuisance defects during the yield ramp of a 5 nm class process.

Why it matters

Review turns a list of coordinates into knowledge of what is going wrong, and that is what lets a fab fix it. Defect review and classification engineers run the tools and recipes, defectivity and yield engineers act on the Paretos, and machine learning engineers build and maintain the classifiers.

In the chip lifecycle, defect review is most intense during process development and yield ramp, when new defect types appear, and it continues through volume production to monitor known defect types and catch excursions early.

It matters most to: Defect Inspection Engineer, Defect Review and Classification Engineer, Defectivity Engineer, ML Engineer, Defect Classification, Yield Enhancement Engineer

Common confusions

Not the same as defect inspection

Inspection scans whole wafers quickly to find possible defects and record their locations. Review looks closely at a chosen subset of those locations to see and classify what is there.

Not the same as failure analysis

Failure analysis investigates why a particular chip failed electrically, often by cutting it open. Defect review images defects on the wafer surface during processing, before any electrical test.

Not the same as a design review

In chip design, a design review is a meeting to check a design against its requirements. Defect review is a measurement step in the fab.

Sources

1. KLA-Tencor Completes Its 45nm Defect Portfolio With New Generation Defect Review and Classification System (press release, 3 July 2007) (opens in a new tab), KLA, 2026-10-22
2. Defect Detection Strategies and Process Partitioning for SE EUV Patterning (Luciana Meli and others, IBM, 24 January 2019) (opens in a new tab), Semiconductor Engineering, 2026-10-22
3. Deep Learning based Defect classification and detection in SEM images: A Mask R-CNN approach (Bappaditya Dey and others, 3 November 2022) (opens in a new tab), arXiv, 2026-10-22
4. Strategies For Faster Yield Ramps On 5nm Chips (Laura Peters, 12 April 2022) (opens in a new tab), Semiconductor Engineering, 2026-10-22

Related terms

• ADC
• Kill ratio
• Bright-field inspection

Where it appears on the Hub

Used on 15 pages of the Hub. In each group, the pages that mention it most come first.