Component · Design & Architecture
Custom layers
The few metal and via layers of a structured ASIC that are made for each customer design on top of a shared base array; the only part of the chip that differs between customers.
- Also known as
- Customisation layers
- Type
- Component
- Domain
- Design & Architecture, Structured ASIC
Overview
In a structured ASIC, almost every layer of the chip is shared between customers: the transistors, the lower metal layers, the clocks, the memories and the input and output cells are all part of the base array. The custom layers are the small number of upper metal and via layers that connect those pre-built resources into one customer's design.
How it works
The vendor fixes in advance which layers are custom. On some platforms only one or a few via layers are custom, and the metal is shared. On others a few top metal layers and their vias are custom.
The customer design is placed and routed onto the base array's resources, and the result is a layout for the custom layers only. Masks are made for those layers, and base wafers held in a wafer bank are finished with them. Because fewer masks are made and the base is already processed, cost and turnaround are lower than for a standard cell chip.
A later change to the design can often be made by changing the custom layers alone, which is why metal changes are routine on structured ASICs.
Examples
- Via programmable platforms change only via layers; metal programmable ones also change metal.
- A customer design finished on banked base wafers with its own top metal and via masks.
- A late logic fix made in the custom layers only.
- Two customer designs on the same base array that differ only in their custom layers.
Why it matters
The custom layers are where the cost, schedule and flexibility of a structured ASIC come from. Fewer custom layers mean fewer masks and a faster turnaround, but also less freedom in routing and density. Structured ASIC designers, mask and fab engineers and programme managers plan around them.
In the structured ASIC lifecycle, the custom layers are designed during customer implementation, signed off before tape-out, and made when the banked wafers are finished.
It matters most to: ASIC Design Engineer (Structured and Custom Digital), FPGA-to-ASIC Conversion Engineer, Physical Design Engineer
Common confusions
- Not the same as the base array
- The base array is shared by every customer and is designed and qualified once. The custom layers are made new for each customer design.
- Not the same as a metal ECO
- A metal ECO is a late change made in the metal layers. On a structured ASIC every design is made in its custom layers, so the first version and later fixes use the same layers.
Sources
- Structured ASIC platform (opens in a new tab), Wikipedia, 2026-11-10
- Designing via-configurable logic blocks for regular fabric (IEEE Transactions on VLSI Systems) (opens in a new tab), VLSI CAD Lab, University of California, Santa Barbara, 2026-11-10
- Impact of Custom Interconnect Masks on Cost and Performance of Structured ASICs (PhD thesis, Usman Ahmed, 2011) (opens in a new tab), University of British Columbia, 2026-11-10
Related terms
Part of the Design & Architecture glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 9 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
- Base Array Architecture (Structured ASIC lifecycle)
- Custom Layer Tape-out (Structured ASIC lifecycle)
- Base array architecture freeze (Structured ASIC lifecycle)
- Base Array Verification & Design Kit (Structured ASIC lifecycle)
- Base Layer Tape-out & Wafer Banking (Structured ASIC lifecycle)
- Custom layer tape-out (Structured ASIC lifecycle)
- and 3 more
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary