CDR (Clock and Data Recovery)

Notes

Most high-speed links use a bang-bang (Alexander) phase detector; long runs of identical bits starve the CDR, which is why data is scrambled or line-coded.

Overview

CDR, short for clock and data recovery, is the receiver function in a serial link that extracts a sampling clock from the incoming data stream itself, because no separate clock is sent, and keeps that clock aligned so that each bit is sampled near the centre of the data eye. Serial interfaces such as PCI Express, Ethernet and USB rely on it. A CDR works much like a phase-locked loop, but it must cope with input that has no transitions for some bits.

How it works

The receiver samples the incoming signal with one or more clocks. A phase detector compares the data transitions with the recovered clock and decides whether the clock is early or late. Linear phase detectors give an output proportional to the phase error; binary or bang-bang detectors, such as the Alexander type, which takes two data samples and one edge sample per bit, give only its sign and are the most common. Baud-rate detectors such as the Mueller-Muller type need just one sample per symbol.

The phase detector's output drives a loop that moves the sampling clock. In a PLL-based CDR it tunes a voltage-controlled oscillator through a loop filter. In a dual-loop CDR, a shared PLL produces a clean clock and each lane uses phase interpolators, sometimes fed by a DLL, to shift that clock to the right phase. Because random data contains runs without transitions, the phase detector gets no information during those runs, so links limit run lengths through line coding.

A CDR is judged by its jitter behaviour. Jitter transfer is how much input jitter appears on the recovered clock, jitter generation is the jitter the CDR adds itself, and jitter tolerance is how much sinusoidal jitter it can follow while still meeting the target bit error rate. Loop bandwidth trades tracking against filtering, and in simulation models the update threshold sets it: a higher threshold gives a steadier clock but slower convergence.

Examples

• A 56 Gb/s PAM4 receiver with a PLL-based CDR using a bang-bang phase detector, described in an IEEE journal paper.
• A multi-lane transceiver in which one PLL is shared and each lane recovers its own phase with phase interpolators.
• A jitter tolerance test that sweeps the frequency of injected sinusoidal jitter and records the largest amount the receiver can handle.
• A link simulation using the MathWorks SerDes Toolbox CDR block with a bang-bang phase detector and a set phase step.

Why it matters

Without a working CDR, a serial link cannot receive data at all, and CDR jitter tolerance is one of the tests that interface standards and customers check. SerDes analogue and digital designers, PHY designers, high-speed interface architects and validation engineers all work on it.

Related terms

• SerDes
• Jitter tolerance
• Bang-bang phase detector
• Scrambling

Where it appears on the Hub

Used on 6 pages of the Hub. In each group, the pages that mention it most come first.