Also known as: SerDes Architect; I/O Architect; High-Speed Interface Architect; PCIe/Ethernet Architect
See this role on the Chiplet lifecycle or on the AI accelerator lifecycle or on the Memory lifecycle or on the Photonics lifecycle or on the SoC lifecycle or on the Soft IP lifecycle
Architects the chip's external high-speed interfaces — PCIe, CXL, Ethernet, USB, MIPI, DDR PHY and die-to-die links — so that bandwidth, latency, reach and compliance targets are met across the package and board channel. Owns where the chip meets the rest of the system.
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