This thread is for discussing the lifecycle document "Process Development & Integration: stage guide".
How the wafer process for a power device is developed and frozen: implantation and activation, gate oxide and interface treatment, trench etch where used, contacts, passivation, thinning and backside metal, joined into one flow with its controls. It is for process integration and unit process engineers, fab, yield, device and quality engineers.
Read the document: https://www.thesemiconhub.com/lifecycle/power-compound/pwr-process-development/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.