1. Purpose and scope
Many power device makers develop and own their wafer process, because ratings and ruggedness depend directly on it. In silicon carbide, dopants are implanted at high temperature and activated by an anneal at temperatures far above those used in silicon; the gate oxide and its interface with the crystal set channel mobility and threshold stability; ohmic contacts and Schottky contacts need their own anneals; and wafers are thinned and given backside metal to cut on-resistance and suit die attach. Gallium nitride devices depend on passivation, field plates and gate stack processes. Silicon IGBTs depend on backside implants and anneals for the field stop and collector.
The purpose of this stage is to develop each of these steps, join them into an integrated flow that builds the device structure targets, and freeze a process baseline with the controls that keep it stable. The process FMEA started here is the basis of the control plan customers will later approve.
In scope: unit process development, integration, short-loop and full-flow lots, the process flow, the process baseline, the process FMEA, the first process control plan and line readiness. Out of scope: the device design, which is frozen before or alongside, and the characterisation of finished devices, which follows.
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