This thread is for discussing the lifecycle document "Pattern Generation & Conversion: stage guide".
How the test patterns are produced: test rule checks, ATPG for the agreed fault models with compression, BIST and boundary scan patterns, functional pattern capture, conversion to the tester format and simulation with tester timing. For ATPG, DFT and test methodology engineers.
Read the document: https://www.thesemiconhub.com/lifecycle/test-program/tp-pattern-generation/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.