This thread is for discussing the lifecycle document "Die-to-Die Interface Design: stage guide".
How the links between dies are defined and how the bump map shared by every die and the package is agreed. Written for interface architects, PHY designers, package designers, test engineers and the assembly supplier's engineers, who must all baseline one definition before the dies and the package are designed in parallel.
Read the document: https://www.thesemiconhub.com/lifecycle/chiplet/chiplet-d2d-interface/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.