This thread is for discussing the lifecycle document "AMS Verification: stage guide".
How an analog or mixed-signal circuit is proved against its specification before layout: process, voltage and temperature corners, Monte Carlo statistics, behavioural model validation and mixed-signal simulation with the surrounding digital logic. For verification engineers, designers and the SoC teams that rely on the models.
Read the document: https://www.thesemiconhub.com/lifecycle/ams/ams-verification/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.