Roles / TSV Process Engineer

TSV Process Engineer

PKG-010v1

Advanced Packaging & AssemblyManufacturingIC3–IC6Individual contributor

Also known as: Through-Silicon Via Engineer; TSV Integration Engineer; Via-Middle Process Engineer

See this role on the Chiplet lifecycle or on the Memory lifecycle or on the Package technology lifecycle or on the SoC lifecycle

Summary

Develops and sustains through-silicon via formation — deep silicon etch, liner and barrier deposition, copper fill, CMP reveal and backside processing — enabling vertical interconnect in interposers, HBM stacks and 3D logic. Owns via integrity as an electrical, mechanical and contamination problem simultaneously.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Project

Work done for a product or program.

Develop deep reactive ion etch processes achieving target via aspect ratio with controlled sidewall profile, scallop depth and bottom roughness.
Qualify liner, barrier and seed deposition into high-aspect-ratio vias, ensuring step coverage and preventing copper diffusion into silicon.
Optimise via copper fill by electroplating with additive chemistry tuned to eliminate seams and voids.
Own copper overburden CMP and backside via reveal, controlling copper protrusion or recess to the bonding requirement.
Characterise and mitigate the copper pumping and keep-out zone effect on adjacent transistor performance.
Establish TSV electrical test structures for resistance, leakage, capacitance and open/short screening at wafer sort.
Control metal contamination and mobile-ion risk introduced by copper in the backend-of-line environment.
Drive TSV reliability characterisation including thermal cycling-induced via extrusion, interface delamination and electromigration in via chains.
Integrate TSV flow with wafer thinning, temporary carrier bonding and backside bump or pad formation.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Reduce TSV cost and cycle time through etch rate improvement, chemistry reuse and reduced metrology sampling.

Major tasks

Project

Produce and hand over the role's key deliverables
- TSV module process specification and recipe set
- Via fill void-free capability report with cross-sections
- Backside reveal and copper protrusion control plan
- TSV electrical test structure definition and wafer sort limits
- Keep-out zone design rule recommendation
- TSV reliability characterisation report
Introduce new productsGeneral
- Set up and qualify the process
- Transfer it to production
- Support the ramp
Keep production in controlGeneral
- Monitor statistical process control charts
- Contain excursions
- Close corrective actions

Function

Maintain the process baselineGeneral
- Keep specifications and control plans current
- Manage changes through change control
Improve the operationGeneral
- Reduce cost and cycle time
- Work with suppliers on quality

Works with

3D stacking and hybrid bonding engineers
interposer integration engineers
fab etch/deposition/CMP module owners
device and reliability engineers
metrology engineers
equipment suppliers
contamination control

Typical backgrounds

MS or PhD in Chemical Engineering, Materials Science, Physics or Electrical Engineering; 5–14 years in wafer fab etch, deposition or CMP process engineering, with 3D integration exposure.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

3 / 5

Remote feasibility

Low

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Hsinchu, Hillsboro, Dresden, Leuven, Icheon and Cheongju, Yokkaichi, Singapore, Albany, Grenoble

Certifications / standards training

SEMI equipment and safety standards; Six Sigma Black Belt; JEDEC reliability test methods

Transfers to (industries)

MEMS and CMOS image sensor fabrication, photonic integrated circuits, microfluidic device manufacturing, quantum device fabrication

Risk if vacant

Vertical interconnect for interposers and stacked memory loses its process owner, with via voiding and copper contamination risks migrating silently into high-value assemblies.

TSV Process Engineer

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

Register or sign in to read on