Roles / RAS Architect

RAS Architect

ARC-019v1

System & SoC ArchitectureArchitectureIC5–IC8Individual contributor

Also known as: Reliability, Availability and Serviceability Architect; Error Handling Architect; Silicon Resiliency Architect

See this role on the AI accelerator lifecycle or on the Space lifecycle or on the SoC lifecycle or on the Soft IP lifecycle

Summary

Designs how the chip detects, contains, reports and recovers from hardware errors so that large fleets keep running and failures are diagnosable. Critical for data-center, telecom and automotive parts where uncorrected errors are unacceptable.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Project

Work done for a product or program.

Define the RAS architecture covering error detection, correction, containment, logging and recovery across every subsystem.
Specify ECC schemes for caches, SRAMs, DRAM and links, and poison propagation rules for uncorrectable data.
Architect the error reporting hierarchy including error records, Arm RAS extension registers, MCA banks and interrupt routing.
Quantify FIT rates from soft-error and hard-failure models and demonstrate that silent data corruption targets are met.
Specify link-level retry, lane degradation and dynamic reconfiguration behaviour for high-speed and die-to-die interfaces.
Define memory page retirement, core offlining and fail-in-place strategies that keep systems running after a fault.
Plan error injection capability in hardware so customers and validation teams can exercise every recovery path.
Analyse field return and fleet telemetry data to determine which RAS features actually catch real failures.
Align RAS capabilities with hyperscaler and telecom customer requirements and represent them in standards bodies.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Define firmware-first versus OS-first error handling policy and the software contract for each error class.

Major tasks

Project

Produce and hand over the role's key deliverables
- RAS architecture specification and error taxonomy
- ECC and poison propagation scheme definition
- Error record and reporting register specification
- FIT rate and silent data corruption budget analysis
- Error injection capability specification
- Firmware and OS error handling interface contract
Define the architectureGeneral
- Collect and clarify the product requirements
- Build performance and power models
- Write and baseline the architecture specification
Support implementationGeneral
- Answer specification questions from design and verification
- Assess the impact of proposed changes
- Compare results with the original targets

Function

Build the architecture practiceGeneral
- Keep modelling tools and reference models current
- Publish design guidelines and specification templates
Plan aheadGeneral
- Study workload and technology trends
- Contribute to the product roadmap

Works with

SoC architects
memory subsystem and coherency architects
firmware and BMC teams
OS kernel engineers
reliability and qualification
hyperscaler and telecom customers
field quality

Typical backgrounds

MS or PhD in Electrical/Computer Engineering; 8–18 years across server silicon design, reliability engineering or memory subsystem architecture.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

5 / 5

Remote feasibility

High

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Austin and Santa Clara USA; Bangalore India; Haifa Israel; Shanghai China; Hsinchu Taiwan; Cambridge UK; Seoul South Korea

Certifications / standards training

—

Transfers to (industries)

Server and storage systems engineering, hyperscale site reliability engineering, telecom network equipment, aerospace fault-tolerant computing

Risk if vacant

Errors go undetected or unreported, silent data corruption reaches customer fleets, and the part is disqualified from data-center and telecom sockets.

RAS Architect

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

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