Roles / Hardware Security Evaluation Engineer

Hardware Security Evaluation Engineer

QSS-019v1

Quality, Reliability, Functional Safety & Product SecurityQualityIC3–IC6Individual contributor

Also known as: Side-Channel Analysis Engineer; Fault Injection Engineer; Hardware Penetration Test Engineer

See this role on the Security lifecycle or on the Vehicle cybersecurity lifecycle or on the SoC lifecycle

Summary

Attacks the company's own silicon in the lab, using side-channel, fault injection and invasive techniques, so that weaknesses are found internally before a certification lab or an adversary finds them.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Project

Work done for a product or program.

Plan and execute differential and correlation power analysis and electromagnetic analysis campaigns against crypto implementations.
Run fault injection attacks using voltage and clock glitching, electromagnetic pulse and laser fault injection on decapsulated devices.
Perform test vector leakage assessment to quantify leakage before full key-recovery attempts.
Attack secure boot, debug authentication and lifecycle transitions through protocol abuse and timing manipulation.
Conduct semi-invasive and invasive analysis including optical probing, microprobing and FIB circuit edit where justified.
Benchmark countermeasure effectiveness across product generations and technology nodes.
Support external evaluation labs by reproducing their findings and pre-empting their test plans.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Rate findings with JIL attack potential methodology and translate them into remediation requirements for design teams.
Build and maintain lab automation: trace capture, alignment, preprocessing and key-recovery pipelines.
Publish internal attack knowledge, threat intelligence and hardening guidance to architects and IP owners.

Major tasks

Project

Produce and hand over the role's key deliverables
- Attack campaign reports with trace counts and success criteria
- Leakage assessment results and countermeasure effectiveness comparisons
- Attack potential ratings and remediation requirement lists
- Lab automation scripts and reusable attack setups
- Internal hardening guidance and threat briefings
Qualify the productGeneral
- Write the qualification plan
- Run stress tests and analyse the results
- Approve the qualification report
Handle quality issuesGeneral
- Analyse failures
- Drive corrective and preventive action
- Respond to customers

Function

Run the quality systemGeneral
- Maintain procedures and records
- Prepare for and run audits
Report and improveGeneral
- Track quality metrics
- Lead improvement projects

Works with

Hardware cryptography engineers
product security architect and engineers
failure analysis lab
certification engineers
external ITSEFs
PSIRT

Typical backgrounds

MS or PhD in electrical engineering, computer science or cryptography; 3–12 years in hardware security evaluation or an ITSEF lab.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

4 / 5

Remote feasibility

Low

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Delft, Graz, Munich, Paris, Bochum, Singapore, Shanghai, Bengaluru, San Jose, Tokyo

Certifications / standards training

Common Criteria evaluator training; Riscure or eShard side-channel and fault injection training; OSCP (optional)

Transfers to (industries)

Payment and smartcard evaluation labs, government security agencies, defence red teams, automotive security testing houses, hardware wallet vendors

Risk if vacant

Countermeasures ship unverified and the first realistic attack assessment happens at a certification lab or in public research, after silicon is frozen.

Hardware Security Evaluation Engineer

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

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