Roles / Formal Verification Engine Developer

Formal Verification Engine Developer

EDA-005v1

EDA, CAD & Design InfrastructureSoftwareIC3–IC7Individual contributor

Also known as: Formal Engine R&D Engineer; Equivalence Checking Engine Developer; Model Checking Engineer

Summary

Builds the SAT, BDD and model-checking engines behind logic equivalence checking and formal property verification so designs can be proven correct rather than only simulated.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Project

Work done for a product or program.

Implement and tune SAT solvers, SMT integrations and BDD packages with clause learning, restarts and portfolio strategies for hardware problems.
Develop bounded and unbounded model checking algorithms including IC3/PDR, interpolation, k-induction and abstraction refinement.
Build combinational and sequential equivalence checking flows that handle retiming, pipeline, and datapath transformations in LEC.
Develop abstraction, localisation and case-splitting heuristics to raise proof convergence on multi-million-gate blocks.
Support SystemVerilog Assertions semantics, constraint solving and coverage of unreachable states.
Build counterexample generation and minimisation so users get short, debuggable failure traces in waveform viewers.
Benchmark proof convergence and runtime against competitor engines and previous releases on industrial property suites.
Debug inconclusive proofs and false failures reported by customers and turn them into engine improvements.
Track academic advances from CAV, FMCAD and the hardware model checking competition and productise promising techniques.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Implement automatic proof orchestration that selects engines per property and manages compute budget across a farm.

Major tasks

Project

Produce and hand over the role's key deliverables
- Proof engine and solver code in the shipping product
- Proof convergence and runtime benchmark reports
- Engine orchestration and strategy library
- Counterexample minimisation capability
- Formal signoff qualification evidence for safety-related use
Develop the softwareGeneral
- Design to the hardware specification
- Write and review the code
- Test on models, emulation or silicon
Release and supportGeneral
- Package and document releases
- Fix customer-reported defects

Function

Maintain the platformGeneral
- Keep build, test and release tools working
- Track toolchain and operating system changes
Raise qualityGeneral
- Run code reviews
- Extend automated tests

Works with

Formal verification users
DV methodology teams
synthesis engine developers
application engineers
safety certification teams

Typical backgrounds

MS/PhD in CS or EE specialising in formal methods, logic or algorithms; 3–15 years in formal tool R&D

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

4 / 5

Remote feasibility

High

Semis core vs. portable

Semis-primary, transfers

Geographic hotspots

Silicon Valley, Austin, Noida, Haifa, Grenoble, Munich, Cambridge UK, Shanghai

Certifications / standards training

—

Transfers to (industries)

Safety-critical software verification, automotive and avionics software toolchains, cryptographic protocol verification, compiler validation

Risk if vacant

Proof convergence and capacity stagnate, so customers fall back to simulation and safety or security signoff claims become unsupportable.

Formal Verification Engine Developer

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

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