Roles / Electrical Characterization Engineer

Electrical Characterization Engineer

PSI-009v1

Silicon Bring-up, Validation & ReliabilityTestIC3–IC6Individual contributor

Also known as: Silicon Characterization Engineer; Device Characterization Engineer; Bench Characterization Engineer

See this role on the AMS lifecycle or on the Process node lifecycle or on the PDK lifecycle or on the Test program lifecycle or on the Startup lifecycle or on the Space lifecycle or on the Power and compound lifecycle or on the MEMS and sensors lifecycle or on the RF lifecycle or on the Hard IP lifecycle or on the SoC lifecycle

Summary

Measures the real electrical behaviour of silicon — DC parameters, AC timing, analog performance and distributions across lots — to establish the numbers that go into the datasheet and the production test limits.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Project

Work done for a product or program.

Characterise DC parameters including leakage, input thresholds, output drive strength, IDDQ and supply current across voltage and temperature.
Measure AC timing parameters such as setup/hold, propagation delay, rise/fall times and jitter against specification and SPICE prediction.
Characterise analog and mixed-signal blocks for PLL jitter, ADC/DAC INL/DNL and SNDR, bandgap accuracy, LDO line and load regulation.
Design characterisation experiments across corner lots (SS, TT, FF) and split wafers to capture true process variation.
Statistically analyse distributions to set datasheet min/typ/max limits with defined sigma margin and guardband.
Correlate bench measurements against ATE measurements and against pre-silicon SPICE and Monte Carlo simulation results.
Build automated characterisation sequences with SMUs, source measure units and precision instruments under program control.
Feed characterisation results into datasheet generation, production test limit setting and design margin reviews.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Document measurement methodology and uncertainty budgets so results are reproducible across labs and sites.

Major tasks

Project

Produce and hand over the role's key deliverables

Characterization report per parameter with distributions and corner data
Datasheet parameter table with justified min/typ/max limits
Bench-to-ATE correlation study
Automated characterization test sequences
Measurement methodology and uncertainty documentation

Develop the test solutionGeneral

Define the test plan and coverage targets
Write and debug the test program
Design or specify the test hardware

Release to productionGeneral

Correlate results across testers and sites
Optimise test time
Release the program under change control

Function

Maintain test infrastructureGeneral
- Keep program libraries and standards current
- Plan tester and hardware capacity
Improve methodsGeneral
- Review escapes and adjust coverage
- Develop data analysis tools

Works with

Analog and mixed-signal designers
product engineering
test engineering
reliability
marketing and datasheet owners
foundry PDK teams

Typical backgrounds

BS/MS in Electrical Engineering with analog or device focus; 3–12 years in characterisation, analog design or product engineering.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

2 / 5

Remote feasibility

Low

Semis core vs. portable

Semis-primary, transfers

Geographic hotspots

Santa Clara, Dallas, Bangalore, Munich, Villach, Hsinchu, Singapore, Tokyo, Grenoble

Certifications / standards training

—

Transfers to (industries)

Precision instrumentation, power electronics module suppliers, sensor manufacturers, metrology and calibration laboratories, photovoltaics

Risk if vacant

Datasheet numbers become guesses carried over from simulation, production limits are set without silicon evidence, and either yield is given away or customers see out-of-spec parts.

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