Roles / CMP Process Engineer

CMP Process Engineer

FAB-006v1

Process Technology & Fab OperationsManufacturingIC2–IC6Individual contributor

Also known as: Chemical Mechanical Planarization Engineer; Polish Process Engineer; CMP Module Engineer

See this role on the Process node lifecycle or on the Memory lifecycle or on the MEMS and sensors lifecycle or on the SoC lifecycle

Summary

Delivers globally and locally planar wafers at every polish step so downstream lithography has depth of focus and interconnect layers are free of dishing, erosion and residue.

A day in the life

Work in progressNo day-in-the-life description has been written for this role yet. If you do this work, we would welcome yours. Suggest a source or a correction

Responsibilities

Lines tagged General are the Hub's general description of this kind of role, used where the role register has no entry yet. They are kept under review and will be refined.

Project

Work done for a product or program.

Develop and release CMP processes for oxide, tungsten, copper, cobalt, poly and STI applications, tuning pressure, platen/head speed, slurry flow and conditioning.
Control removal rate, within-wafer non-uniformity, dishing, erosion and step height against integration planarity budgets.
Qualify slurries, pads, conditioning discs and post-CMP cleaning chemistries with suppliers such as CMC Materials, Fujimi, DuPont and Hitachi Chemical.
Eliminate CMP-specific defects including scratches, micro-scratches, slurry residue, corrosion, delamination and pattern peeling.
Implement endpoint detection via motor current and optical monitoring, and set up run-to-run removal-rate control loops.
Manage pad life, conditioning recipes and consumable change criteria to stabilise removal rate over the pad lifetime.
Analyse pattern-density dependence of polish and feed layout-density guidance back to design enablement and integration.
Own post-CMP cleaning and brush-scrub performance to keep particles and metal contamination inside limits.
Drive cost-per-wafer reduction on slurry consumption, pad lifetime and water/waste treatment load.
Support excursion response for planarity and scratch-driven yield loss with containment and corrective action.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

Maintain process specifications, control plans and work instructions.General
Work with equipment and material suppliers on performance and quality.General
Improve cost, cycle time and yield across the operation.General

Major tasks

Project

Produce and hand over the role's key deliverables
- Released CMP recipes and planarity specifications
- Removal rate stability and pad-life qualification data
- Slurry and consumable qualification reports
- Scratch and residue defect reduction plan
- Pattern-density polish guidance for design and integration
Introduce new productsGeneral
- Set up and qualify the process
- Transfer it to production
- Support the ramp
Keep production in controlGeneral
- Monitor statistical process control charts
- Contain excursions
- Close corrective actions

Function

Maintain the process baselineGeneral
- Keep specifications and control plans current
- Manage changes through change control
Improve the operationGeneral
- Reduce cost and cycle time
- Work with suppliers on quality

Works with

Films and etch module engineers
wet clean
process integration
defect inspection
equipment engineering
slurry suppliers
facilities waste treatment

Typical backgrounds

BS/MS in Chemical Engineering, Mechanical Engineering, Materials Science or Chemistry; 2–12 years in a wafer fab CMP module.

Demand signal

0 open listings right now
0 Talent Wafer employer inquiries

Counts live listings tagged to this role, and employer interest in candidates from Talent Wafer runs for this role (all runs to date). Hub activity only, not the wider market.

Comp tier (within semis)

3 / 5

Remote feasibility

Low

Semis core vs. portable

Core semiconductor-only

Geographic hotspots

Hsinchu and Tainan, Taiwan; Hillsboro and Boise, USA; Cheongju and Hwaseong, South Korea; Dresden, Germany; Singapore; Yokkaichi, Japan

Certifications / standards training

Chemical handling and wastewater awareness training; Six Sigma Green Belt; SEMI S2 safety

Transfers to (industries)

Sapphire and SiC substrate polishing, optical component finishing, hard disk substrate manufacturing, precision surface finishing and abrasives suppliers

Risk if vacant

Planarity and scratch control degrade quickly, starving downstream lithography of depth of focus and creating interconnect shorts and opens.

CMP Process Engineer

Summary

A day in the life

Responsibilities

Project

Function

Major tasks

Project

Function

Works with

Register or sign in to read on