News / Markets & Policy / HARE: Fast Read Disturbance Threshold Profiling in Modern DRAM Chips via Reduced Timing Constraints
HARE: Fast Read Disturbance Threshold Profiling in Modern DRAM Chips via Reduced Timing Constraints
By The Semiconductor Hub news desk ·
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Modern DRAM chips are vulnerable to read disturbance, which manifests as bitflips in a victim row physically near an aggressor row that is repeatedly activated. State-of-the-art mitigations rely on accurate and exhaustive profiling of the read disturbance threshold (RDT), i.e., the minimum number of aggressor row activations needed to induce the first bitflip. However, RDT changes significantly and unpredictably over time, motivating online profilers that dynamically adjust a mitigation's RDT c…
Read at arXiv cs.AR (Hardware Architecture)Source: arXiv cs.AR (Hardware Architecture), published . The summary is the Hub's own; the full story is at the source. Report a rights or accuracy concern