Fully unrolled, parameterized SPECK cipher in Verilog (All 10 variants in one file)

Hey everyone, I recently updated CipherCore — open-source collection of reusable, Verilog crypto cores — with a new implementation of the SPECK lightweight block cipher. Instead of writing separate modules for every block/key size, the goal here was maximum parameterization. Here is a quick breakdown of what’s under the hood: One File, 10 Variants: A single source file covers all ten SPECK configurations (from Speck32/64 all the way up to Speck128/256). The specific variant is selected purely b…

Source: r/chipdesign, published 2026-10-31. The summary is the Hub's own; the full story is at the source. Report a rights or accuracy concern