CAPER: Circuit-Aware Parameter-Efficient Reasoning in LLMs for Analog Verification

Large language models (LLMs) are increasingly used to generate analog circuits, yet every netlist must also be verified. We propose LLMs as verification assistants for analog circuits that flag unmet specifications and reliability issues that appear under process, voltage, and temperature (PVT) variation. These issues emerge from how circuit stages combine, a structure that generic parameter-efficient fine-tuning (PEFT) methods such as LoRA do not capture. To this end, we introduce CAPER, a cir…

Source: arXiv cs.AR (Hardware Architecture), published 2026-11-03. The summary is the Hub's own; the full story is at the source. Report a rights or accuracy concern