News / EDA & Tools / An Agentic Python Framework for LLM-Driven UVM Testbench Synthesis with Closed-Loop Compiler Feedback
An Agentic Python Framework for LLM-Driven UVM Testbench Synthesis with Closed-Loop Compiler Feedback
By The Semiconductor Hub news desk ·
Link post
Protocol bridge verification is a persistent bottleneck in SoC development: for every new bridge instance, engineers hand-craft a full UVM testbench from scratch, consuming 40--100 engineering hours of bring-up effort. We present an agentic Python framework that generates complete, protocol-aware UVM testbenches for arbitrary IP and subsystem configurations from a structured Verification Manifest---a JSON specification encoding interface topology, protocol semantics, and coverage intent. The fr…
Read at arXiv cs.AR (Hardware Architecture)Source: arXiv cs.AR (Hardware Architecture), published . The summary is the Hub's own; the full story is at the source. Report a rights or accuracy concern